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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9731 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 10-bit, 170 msps d/a converter functional block diagram analog return iout iout d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clock ref in amp out decoders and drivers register switch network ttl drive logic control amp internal voltage reference r set ref out control amp in digital Cv s digital +v s analog Cv s features 170 msps update rate ttl/high-speed cmos-compatible inputs wideband sfdr: 66 db @ 2 mhz/50 db @ 65 mhz pin-compatible, lower cost replacement for industry standard ad9721 dac low power: 439 mw @ 170 msps fast settling: 3.8 ns to 1/2 lsb internal reference two package styles: 28-lead soic and ssop applications digital communications direct digital synthesis waveform reconstruction high speed imaging 5 mhzC65 mhz hfc upstream path general description the AD9731 is a 10-bit, 170 msps, bipolar d/a converter that is optimized to provide high dynamic performance, yet offer lower power dissipation and more economical pricing than afforded by previous bipolar high performance dac solutions. the AD9731 was designed primarily for demanding communi- cations systems applications where wideband spurious-free dynamic range (sfdr) requirements are strenuous and could previously only be met by using a high performance dac such as the industry-standard ad9721. the proliferation of digital communications into basestation and high volume subscriber- end markets has created a demand for excellent dac perfor- mance delivered at reduced levels of power dissipation and cost. the AD9731 is the answer to that demand. optimized for direct digital synthesis (dds) waveform recon- struction, the AD9731 provides 50 db of wideband harmonic suppression over a dc-to-65 mhz analog output bandwidth. this signal bandwidth addresses the transmit spectrum in many of the emerging digital communications applications where signal purity is critical. narrowband, the AD9731 provides an sfdr of greater than 79 db. this excellent wideband and narrowband ac performance, coupled with a lower pricing struc- ture, make the AD9731 the optimum high performance dac value. the AD9731 is packaged in 28-lead soic (same footprint as the industry standard ad9721) and super space-saving 28-lead ssop; both are specified to operate over the extended industrial temperature range of C40 c to +85 c.
C2C rev. 0 AD9731Cspecifications (+v s = +5 v, Cv s = C5.2 v, clock = 125 mhz, r set = 1.96 k v for 20.4 ma i out , v ref = C1.25 v, unless otherwise noted.) parameter temp test level min typ max units resolution 10 bits throughput rate +25 c iv 165 170 mhz dc accuracy differential nonlinearity +25 c i 0.25 1 lsb full vi 0.35 1.5 lsb integral nonlinearity +25 c i 0.6 1 lsb full vi 0.7 1.5 lsb initial offset error zero-scale offset error +25 c i 35 70 m a full vi 40 100 m a full-scale gain error 1 +25 c i 2.5 5 % fs full vi 2.5 5 % fs offset drift coefficient v 0.04 m a/ c reference/control amp internal reference voltage 2 +25 c i C1.35 C1.25 C1.15 v internal reference voltage drift full iv 100 m v/ c internal reference output current 3 full vi C50 +500 m a amplifier input impedance +25 cv 50 k w amplifier bandwidth +25 c v 2.5 mhz reference input 4 reference input impedance +25 c v 4.6 k w reference multiplying bandwidth 5 +25 c v 75 mhz output performance output current 4, 6 +25 c v 20 ma output compliance +25 c iv C1.5 +3 v output resistance +25 c v 240 w output capacitance +25 cv 5 pf voltage settling time to 1/2 lsb (t st ) 7 +25 c v 3.8 ns propagation delay (t pd ) 8 +25 c v 2.9 ns glitch impulse 9 +25 c v 4.1 pvs output slew rate 10 +25 c v 400 v/ m s output rise time 10 +25 cv 1 ns output fall time 10 +25 cv 1 ns digital inputs input capacitance full iv 2 pf logic 1 voltage full vi 2.0 v logic 0 voltage full vi 0.8 v logic 1 current +25 cvi 8 50 m a logic 0 current +25 c vi 30 100 m a minimum data setup time (t s ) 11 +25 c iv 1.2 2 ns full iv 1.5 2.5 ns minimum data hold time (t h ) 12 +25 c iv 0.1 1.0 ns full iv 0.1 1.0 ns clock pulsewidth low (pw min ) +25 civ 2 ns clock pulsewidth high (pw max ) +25 civ 2 ns sfdr performance (wideband) 13 2 mhz a out +25 cv 66 db 10 mhz a out +25 cv 62 db 20 mhz a out +25 cv 61 db 40 mhz a out +25 cv 55 db 65 mhz a out (clock = 170 mhz) +25 cv 50 db 70 mhz a out (clock = 170 mhz) +25 cv 47 db
C3C rev. 0 AD9731 parameter temp test level min typ max units sfdr performance (narrowband) 13 2 mhz; 2 mhz span +25 cv 79 db 25 mhz, 2 mhz span +25 cv 61 db 10 mhz, 5 mhz span (clock = 170 mhz) +25 cv 73 db intermodulation distortion 14 f1 = 800 khz, f2 = 900 khz +25 cv 58 db power supply 15 digital Cv supply current +25 c i 27 37 ma full vi 27 42 ma analog Cv supply current +25 c i 45 53 ma full vi 45 66 ma digital +v supply current +25 c i 13 20 ma full vi 15 22 ma power dissipation +25 c v 439 mw full v 449 mw psrr +25 c v 100 m a/v notes 1 measured as an error in ratio of full-scale current to current through r set (640 m a nominal); ratio is nominally 32. dac load is virtual ground. 2 internal reference voltage is tested under load conditions specified in internal reference output current specification. 3 internal reference output current defines load conditions applied during internal reference voltage test. 4 full-scale current variations among devices are higher when driving reference in directly. 5 frequency at which a 3 db change in output of dac is observed; r l = 50 w ; 100 mv modulation at midscale. 6 based on i fs = 32 (control amp in/r set ) when using internal control amplifier. dac load is virtual ground. 7 measured as voltage settling at midscale transition to 0.1%; r l = 50 w . 8 measured from 50% point of rising edge of clock signal to 1/2 lsb change in output signal. 9 peak glitch impulse is measured as the largest area under a single positive or negative transient. 10 measured with r l = 50 w and dac operating in latched mode. 11 data must remain stable for specified time prior to rising edge of clock. 12 data must remain stable for specified time after rising edge of clock. 13 sfdr is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencie s in the output spectrum window. the frequency span is dc-to-nyquist unless otherwise noted. 14 intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the dac. the distortion products created will manifest themselves at sum and difference frequencies of the two tones. 15 supply voltages should remain stable within 5% for nominal operation. specifications subject to change without notice. code 2 code 3 code 4 code 1 code 2 data code 1 data code 3 data code 4 data t s t h pw min pw max clock data analog output clock analog output t pd t st specified error band h w glitch area = 1/2 height 3 width detail of settling time figure 1. timing diagrams
AD9731 C4C rev. 0 absolute maximum ratings* analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s to +v s +v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . C0.7 v to +v s Cv s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C7 v analog output current . . . . . . . . . . . . . . . . . . . . . . . . 30 ma control amplifier input voltage range . . . . . . . . . 0 v to C4 v reference input voltage range . . . . . . . . . . . . . . . . 0 v to Cv s maximum junction temperature . . . . . . . . . . . . . . . . +150 c operating temperature range . . . . . . . . . . . C40 c to +85 c internal reference output current . . . . . . . . . . . . . . . 500 m a lead temperature (10 sec soldering) . . . . . . . . . . . . . +300 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +165 c control amplifier output current . . . . . . . . . . . . . 2.5 ma *absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. explanation of test levels test level definition i 100% production tested. ii the parameter is 100% production tested at +25 c; sampled at temperature production. iii sample tested only. iv parameter is guaranteed by design and character- ization testing. v parameter is a typical value only. vi all devices are 100% production tested at +25 c; guaranteed by design and characterization testing for industrial temperature range devices. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9731 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package model range description options AD9731br C40 c to +85 c 28-lead wide body (soic) r-28 AD9731brs C40 c to +85 c 28-lead shrink small (ssop) rs-28 AD9731-pcb 0 c to +70 c pcb
AD9731 C5C rev. 0 pin function description pin # pin name pin description 1 d9(msb) most significant data bit of digital input word. 2C9 d8Cd1 eight bits of 10-bit digital input word. 10 d0(lsb) least significant data bit of digital input word. 11 clock ttl-compatible edge-triggered latch enable signal for on-board registers. 12, 13 nc no internal connection to this pin. 14 digital +v s +5 v supply voltage for digital circuitry. 15, 18, 28 gnd converter ground. 16 digital Cv s C5.2 v supply voltage for digital circuitry. 17 r set connection for external reference set resistor; nominal 1.96 k w . full-scale output current = 32 (control amp in v/r set ). 19 analog return analog return. this point and the reference side of the dac load resistors should be con- nected to the same potential (nominally ground). 20 i out analog current output; full-scale current occurs with a digital word input of all 1s. with external load resistor, output voltage = i out (r load i r internal ). r internal is nominally 240 w . 21 i outb complementary analog current output; full-scale current occurs with a digital word input of all 0s. 22 analog Cv s negative analog supply, nominally C5.2 v. 23 ref in normally connected to control amp out (pin 24). direct line to dac current source network. voltage changes (noise) at this point have a direct effect on the full-scale output current of the dac. full-scale current output = 32 (control amp in/r set ) when using the internal amplifier. dac load is virtual ground. 24 control amp out normally connected to ref in (pin 23). output of internal control amplifier which pro- vides a reference for the current switch network. 25 ref out normally connected to control amp in (pin 26). internal voltage reference, nomi- nally C1.25 v. 26 control amp in normally connected to ref out (pin 25) if not connected to external reference. 27 digital Cv s negative digital supply, nominally C5.2 v. pin configuration gnd digital Cv s control amp in ref out control amp out ref in analog Cv s i outb i out analog return gnd r set digital Cv s gnd d8 d7 d9(msb) d6 d5 d4 d3 d2 d1 d0(lsb) clock nc nc digital +v s top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD9731 nc = no connect
AD9731 C6C rev. 0 Ctypical performance characteristics a out C mhz 80 10 sfdr C db 75 70 65 60 55 50 20 30 40 50 60 70 80 figure 2. narrowband sfdr (clock = 170 mhz) vs. a out frequency a out C mhz 80 10 sfdr C db 75 70 65 60 55 50 20 30 40 50 60 85 figure 3. narrowband sfdr (clock = 125 mhz) vs. a out frequency a out C mhz 10 sfdr C db 65 60 55 50 20 30 40 50 60 45 40 70 80 90 figure 4. wideband sfdr (170 mhz clock) vs. a out i out C ma sfdr C db 60 55 50 20 18 10 6 2 45 40 16 14 12 8 4 figure 5. sfdr vs. i out (clock =125 mhz/a out = 40 mhz) lsb 0.4 C0.4 C0.3 C0.2 C0.1 0 0.3 0.2 0.1 figure 6. typical differential nonlinearity performance (dnl) lsb 0.4 C0.6 C0.4 C0.2 0 0.2 0.6 figure 7. typical integral nonlinearity performance (inl)
AD9731 C7C rev. 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 encode = 125mhz a out = 2mhz span = 62.5mhz 1 1 1ap 0hz start 6.25mhz 62.5mhz stop figure 8. wideband sfdr 2 mhz a out ; 125 mhz clock C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 encode = 125mhz a out = 10mhz span = 62.5mhz 1 1 1ap 0hz start 6.25mhz 62.5mhz stop prn figure 9. wideband sfdr 10 mhz a out ; 125 mhz clock C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 encode = 125mhz a out = 20mhz span = 62.5mhz 1 1ap 0hz start 6.25mhz 62.5mhz stop 1 figure 10. wideband sfdr 20 mhz a out ; 125 mhz clock C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 encode = 125mhz a out = 40mhz span = 62.5mhz 1 1 1ap 0hz start 6.25mhz 62.5mhz stop figure 11. wideband sfdr 40 mhz a out ; 125 mhz clock 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 1 1 1ap 0hz start 8.5mhz 85mhz stop figure 12. wideband sfdr 65 mhz a out ; 170 mhz clock C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 1 1 1ap 0hz start 8.5mhz 85mhz stop encode = 170mhz a out = 70mhz span = 85mhz figure 13. wideband sfdr 70 mhz a out ; 170 mhz clock
AD9731 C8C rev. 0 theory and applications the AD9731 high speed digital-to-analog converter utilizes most significant bit decoding and segmentation techniques to reduce glitch impulse and deliver high dynamic performance on lower power consumption than previous bipolar dac technologies. the design is based on four main subsections: the decoder/ driver circuits, the edge-triggered data register, the switch net- work and the control amplifier. an internal bandgap reference is included to allow operation of the device with minimum exter- nal support components. digital inputs/timing the AD9731 has ttl/high speed cmos-compatible single- ended inputs for data inputs and clock. the switching threshold is +1.5 v. in the decoder/driver section, the three msbs are decoded to seven thermometer code lines. an equalizing delay is included for the seven least significant bits and the clock signals. this delay minimizes data skew and data setup and hold times at the register inputs. C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 1 1 1ap 0hz start 200khz 2mhz stop encode = 125mhz a out 1 = 800khz a out 2 = 900khz span = 2mhz figure 14. wideband intermodulation distortion f1 = 800 khz; f2 = 900 khz; 125 mhz clock; span = 2 mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 1 1 1ap 0hz start 6.25mhz 62.5mhz stop encode = 125mhz a out 1 = 800khz a out 2 = 900khz span = 62.5mhz prn figure 15. wideband intermodulation distortion f1 = 800 khz; f2 = 900 khz; 125 mhz clock; span = 62.5 mhz the on-board register is rising-edge triggered and should be used to synchronize data to the current switches by applying a pulse with proper data setup and hold times as shown in the timing diagram. although the AD9731 is designed to provide isolation of the digital inputs to the analog output, some cou- pling of digital transitions is inevitable. digital feedthrough can be minimized by forming a low-pass filter at the digital input by using a resistor in series with the capacitance of each digital input. this common high speed dac application technique has the effect of isolating digital input noise from the analog output. references the internal bandgap reference, control amplifier and reference input are pinned out to provide maximum user flexibility in configuring the reference circuitry for the AD9731. when using the internal reference, ref out (pin 25) should be connected to control amp in (pin 26). control amp out (pin 24) should be connected to ref in (pin 23). a 0.1 m f ceramic capacitor connected from pin 23 to analog Cv s (pin 22) im- proves settling time by decoupling switching noise from the current sink baseline. a reference current cell provides feedback to the control amplifier by sinking current through r set (pin 17). full-scale current is determined by control amp in and r set according to the following equation: i out (fs) = 32( control amp in / r set ) the internal reference is nominally C1.25 v with a tolerance of 8% and typical drift over temperature of 100 ppm/ c. if greater accuracy or temperature stability is required, an external reference can be used. the ad589 reference features 10 ppm/ c drift over the 0 c to +70 c temperature range. two modes of multiplying operation are possible with the AD9731. signals with bandwidths up to 2.5 mhz and input swings from C0.6 v to C1.2 v can be applied to the control amp in pin as shown in figure 16. because the control ampli- fier is internally compensated, the 0.1 m f capacitor discussed above can be reduced to maximize the multiplying bandwidth. however, it should be noted that output settling time, for changes in the digital word, will be degraded. r set C0.6 to C1.2v 2.5mhz typical r t 0.1 m f r set control amp in control amp out reference in AD9731 analog Cv s figure 16. low frequency multiplying circuit
AD9731 C9C rev. 0 the reference in pin can also be driven directly for wider bandwidth multiplying operation. the analog signal for this mode of operation must have a signal swing in the range of C3.3 v to C4.25 v. this can be implemented by capacitively coupling into reference in a signal with a dc bias of C3.3 v (i out ? 22.5 ma) to C4.25 v (i out ? 3 ma), as shown in figure 17, or by dividing reference in with a low impedance op amp whose s ignal swing is limited to the stated range. note: when using an external reference, the external refer- ence voltage must be applied prior to applying Cv s . reference in AD9731 Cv s approx C3.8v Cv s figure 17. wideband multiplying circuit analog output the switch network provides complementary current outputs i out and i outb . the design of the AD9731 is based on statisti- cal current source matching, which provides a 10-bit linearity without trim. current is steered to either i out or i outb in pro- portion to the digital input word. the sum of the two currents is always equal to the full-scale output current minus 1 lsb. the current can be converted to a voltage by resistive loading as shown in the block diagram. both i out and i outb should be equally loaded for best overall performance. the voltage that is developed is the product of the output current and the value of the load resistor. an operational amplifier can also be used to perform the i-to-v conversion of the dac output. figure 18 shows an example of a circuit that uses the ad9617, a high speed, current feedback amplifier. the resistor values in figure 18 provide a 4.096 v swing, centered at ground, at the output of the ad9617 amplifier. ad9617 AD9731 r1 200 v 10k v 1/2 ad708 10k v r2 100 v r fb 400 v i out i outb control amp in ref out r ff 25 v r l 25 v 1/2 ad708 2048v v out i fs i fs 25 v figure 18. i-to-v conversion using a current feedback amplifier evaluation board the performance characteristics of the AD9731 make it ideally suited for direct digital synthesis (dds) and other waveform synthesis applications. the AD9731 evaluation board provides a platform for analyzing performance under optimum layout con- ditions. the AD9731 also provides a reference for high speed circuit board layout techniques.
AD9731 C10C rev. 0 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 r1 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 dgnd dgnd dgnd pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 29 +v dig dgnd r16 50 v d1 u2 r1 u21 d2 d3 d4 d5 d6 d7 d8 d9 d10 dac clock nc1 nc2 +5 dig 1 2 3 4 5 6 7 8 9 10 11 12 13 14 gnd3 digital Cv s control amp in ref out control amp out ref in analog Cv s i out i out ana return gnd1 r set digital Cv s gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 u3 r2 u20 u4 r3 u19 u5 r4 u18 u6 r5 u17 u7 r6 u16 u8 r7 u15 u9 r8 u14 u10 r9 u13 u11 r10 u12 +v dig Cv dig dgnd Cv dig dgnd agnd Cv ana bnc1j2 agnd agnd r15 25 v r14 1960 v agnd c1 0.1 m f c2 10 m f note: r1Cr10 = 50 v AD9731 u1 10 9 8 7 6 5 4 3 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 15 13 11 gnd4 gnd5 gnd6 dgnd gnd Cv +v Cv dig dgnd +v dig 28 27 26 25 24 23 22 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 20 18 16 14 12 +5v1 +5v2 +12v C12v C5v 2 1 ien ii 37 36 35 34 33 32 31 30 e1 e2 e4 e3 +vd Cvd c37drpf con1 dgnd 21 19 17 gnd1 gnd2 gnd3 clock switch matrix jumper source notes e5 to e7 con 1 pin 10 computer provides clock e6 to e8 j1 bnc remove y1 e6 to e8 y1 remove r12 e8 to e10 dg2020 data ext. clk to e7 generator ext. gnd to e9 Cv dig Cva dgnd c7 10 m f c8 0.1 m f c6 0.1 m f c3 10 m f c9 0.1 m f c4 0.1 m f agnd dgnd dgnd pwr out gnd bnc y1 oscillator optional +v dig +v dig +v dig pwr3 4 3 2 c5 0.1 m f dgnd agnd Cv dig Cv ana 12 l2 l1 12 ferrite beads 4.9k v rp2 optional 4.9k v rp1 optional bnc1 dgnd r12 50 v j1 e6 e5 e8 e7 e9 e10 r13 50 v +vd r1 4.9k v bnc figure 19. AD9731-pcb evaluation board schematic
AD9731 C11C rev. 0 outline dimensions dimensions shown in inches and (mm). 28-lead soic wide body (soic) (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-lead shrink small outline (ssop) (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 c3301C8C4/98 printed in u.s.a.

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